Introduction to Microprocessor 8086 - Complete Basics
Welcome to KnowledgeKnot! Master the fundamentals of 8086 microprocessor with detailed coverage of buses, memory architecture, and processor comparisons.
Introduction to 8086 Microprocessor Fundamentals
The Intel 8086 microprocessor is a 16-bit processor introduced in 1978, marking a significant advancement in computing technology. It serves as the foundation for the x86 architecture family that dominates modern computing. Understanding the 8086's fundamental concepts is essential for grasping computer architecture principles.
What is a Microprocessor?
A microprocessor is a programmable digital device that acts as the central processing unit (CPU) of a computer system. It executes instructions, performs calculations, and controls data flow within the system. The microprocessor integrates the arithmetic logic unit (ALU), control unit, and registers on a single integrated circuit chip.
Key Characteristics of 8086
- Technology: 16-bit microprocessor architecture
- Year of Introduction: 1978 by Intel Corporation
- Manufacturing Process: 3-micron HMOS technology
- Package: 40-pin Dual In-line Package (DIP)
- Clock Speed: 5 MHz to 10 MHz variants
- Power Supply: +5V single power supply
- Transistor Count: Approximately 29,000 transistors
Bus System Architecture - Foundation of Communication
The 8086 microprocessor communicates with external devices through a sophisticated bus system consisting of three main buses. Understanding these buses is crucial for comprehending processor operation:
- Address Bus: 20-bit wide, carries memory and I/O addresses
- Data Bus: 16-bit wide, transfers actual data bidirectionally
- Control Bus: Carries control and status signals for coordination
Why Study 8086?
The 8086 remains educationally significant because:
- Architecture Foundation: Basis for all x86 processors (80286, 80386, Pentium series)
- Conceptual Clarity: Simple enough to understand fundamental processor concepts
- Industry Relevance: Many embedded systems still use 8086-compatible processors
- Assembly Language Learning: Excellent platform for learning assembly programming
- Computer Science Education: Standard reference in computer architecture courses
Fundamental Concepts - Memory and Data Organization
Before diving into specific bus details, it's essential to understand how data is organized and accessed in the 8086 system:
- Byte: 8 bits, smallest addressable unit
- Word: 16 bits (2 bytes), natural data size for 8086
- Double Word: 32 bits (4 bytes), used for addresses and large data
- Memory Organization: Linear array of bytes from 00000H to FFFFFH
- Endianness: Little-endian format (LSB at lower address)
Bus Size Implications and System Performance
The width of each bus directly impacts system capabilities and performance characteristics:
- Address Bus Width: Determines maximum addressable memory space
- Data Bus Width: Affects data transfer rate and processing speed
- Control Bus Complexity: Enables system coordination and advanced features
Memory Hierarchy in 8086 Systems
The 8086 typically operates within a memory hierarchy that includes:
- Registers: Fastest access, 16-bit internal storage
- Cache: Not present in basic 8086, added in later processors
- Main Memory (RAM): Primary working space, up to 1MB
- Secondary Storage: Disk drives, accessed through I/O operations
Address Bus - Memory Addressing Foundation
The address bus is a unidirectional bus that carries address information from the processor to memory and I/O devices. In the 8086 microprocessor, the address bus is 20 bits wide, which fundamentally determines the processor's memory addressing capabilities.
Memory Address Calculation Fundamentals
The relationship between address bus width and addressable memory follows a mathematical principle:
Formula: Maximum Addressable Memory = 2^(Address Bus Width in bits)
8086 Memory Addressing Calculation:
Address Bus Width: 20 bits
Maximum Memory: 2^20 = 1,048,576 bytes = 1 MB
Address Range: 00000H to FFFFFH (hexadecimal)
Binary Range: 00000000000000000000₂ to 11111111111111111111₂
Decimal Range: 0 to 1,048,575
Address Bus Width Evolution and Comparison
Understanding how address bus width has evolved helps appreciate the 8086's position in processor development:
| Processor | Year | Address Bus Size | Maximum Memory | Address Range | Significance |
|---|
| 8085 | 1976 | 16 bits | 64 KB | 0000H - FFFFH | Predecessor to 8086 |
| 8086 | 1978 | 20 bits | 1 MB | 00000H - FFFFFH | 16x more memory than 8085 |
| 80286 | 1982 | 24 bits | 16 MB | 000000H - FFFFFFH | Protected mode introduction |
| 80386 | 1985 | 32 bits | 4 GB | 00000000H - FFFFFFFFH | 32-bit computing era |
Practical Memory Addressing Examples
Address Bus Width Impact Examples:
- 4-bit Address Bus: 2^4 = 16 locations (16 bytes)
- 8-bit Address Bus: 2^8 = 256 locations (256 bytes)
- 12-bit Address Bus: 2^12 = 4,096 locations (4 KB)
- 16-bit Address Bus: 2^16 = 65,536 locations (64 KB)
- 20-bit Address Bus: 2^20 = 1,048,576 locations (1 MB)
Address Formation in 8086
The 8086 uses a unique segmented addressing scheme to generate 20-bit addresses from 16-bit segments:
- Segment Address: 16-bit value in segment register
- Offset Address: 16-bit displacement within segment
- Physical Address: (Segment × 10H) + Offset
- Formula: Physical Address = (Segment << 4) + Offset
Data Bus - Information Transfer Highway
The data bus is a bidirectional communication pathway that transfers actual data between the processor, memory, and I/O devices. The width of the data bus is one of the most critical factors determining processor performance and capabilities.
8086 Data Bus Characteristics
The 8086 features a 16-bit data bus, which distinguishes it from its predecessor (8085) and variant (8088):
- Bus Width: 16 bits (2 bytes) wide
- Direction: Bidirectional (read and write operations)
- Data Transfer Rate: 2 bytes per memory access cycle
- Natural Word Size: 16 bits matches processor architecture
- Memory Interface: Requires 16-bit memory organization
Data Bus Impact on System Performance
The data bus width directly affects several aspects of system performance:
- Transfer Bandwidth: Wider bus = more data per transfer cycle
- Execution Speed: Fewer memory accesses needed for larger data
- System Cost: Wider buses require more complex memory systems
- Power Consumption: More data lines increase power requirements
- PCB Complexity: Additional traces and connections needed
Detailed Processor Comparison - Data Bus Architecture
| Processor | Data Bus Width | Word Size | Bytes per Transfer | 16-bit Data Access | Performance Impact |
|---|
| 8085 | 8 bits | 8 bits (1 byte) | 1 byte/cycle | 2 memory accesses | Slower for multi-byte data |
| 8086 | 16 bits | 16 bits (2 bytes) | 2 bytes/cycle | 1 memory access | Optimal for 16-bit operations |
| 8088 | 8 bits | 16 bits (internal) | 1 byte/cycle | 2 memory accesses | Internal 16-bit, external 8-bit |
8086 vs 8088 - Architectural Differences and Implications
Intel 8086 Processor
- External Data Bus: 16 bits wide
- Memory Interface: Direct 16-bit memory connection
- Word Access: Single memory cycle for 16-bit data
- Performance: Higher throughput for data transfers
- System Cost: Higher due to 16-bit memory requirements
- Memory Organization: Even and odd byte banks
- Target Market: High-performance computing systems
- Pin Configuration: 40-pin package with multiplexed AD0-AD15
Intel 8088 Processor
- External Data Bus: 8 bits wide
- Memory Interface: 8-bit memory connection (cost-effective)
- Word Access: Two memory cycles for 16-bit data
- Performance: Lower throughput due to bus bottleneck
- System Cost: Lower due to 8-bit memory compatibility
- Memory Organization: Simple linear byte organization
- Target Market: Cost-sensitive personal computers
- Pin Configuration: 40-pin package with AD0-AD7, A8-A19
Data Transfer Examples and Timing
Example: Transferring 32-bit Data
8086 (16-bit data bus):
- Transfer 1: Lower 16 bits (cycles required: 1)
- Transfer 2: Upper 16 bits (cycles required: 1)
- Total cycles: 2
8088 (8-bit data bus):
- Transfer 1: Bits 0-7 (cycles required: 1)
- Transfer 2: Bits 8-15 (cycles required: 1)
- Transfer 3: Bits 16-23 (cycles required: 1)
- Transfer 4: Bits 24-31 (cycles required: 1)
- Total cycles: 4
Arithmetic Logic Unit (ALU) - The Computational Core
The Arithmetic Logic Unit (ALU) is the computational heart of any microprocessor, responsible for performing all mathematical calculations and logical operations. The ALU's design and capabilities fundamentally define the processor's computational power and data handling characteristics.
8086 ALU Architecture and Specifications
The 8086 features a sophisticated 16-bit ALU that can handle various data types and operations:
- Bit Width: 16-bit ALU for native 16-bit operations
- Data Types Supported: 8-bit bytes, 16-bit words, signed and unsigned integers
- Arithmetic Operations: Addition, Subtraction, Multiplication, Division
- Logical Operations: AND, OR, XOR, NOT, Compare operations
- Bit Manipulation: Shift left/right, Rotate left/right with/without carry
- Special Operations: Increment, Decrement, Negate, ASCII adjustments
Why 8086 is Classified as a 16-bit Processor
The classification of a processor as "16-bit" is primarily determined by the ALU width, though multiple factors contribute:
Primary Classification Criteria:
- ALU Width (Primary Factor): 16-bit ALU can process 16-bit data natively
- Register Size (Supporting Factor): General-purpose registers are 16 bits wide
- Data Bus Width (Performance Factor): 16-bit external data bus
- Instruction Set (Capability Factor): Instructions optimized for 16-bit operands
- Memory Addressing (Scope Factor): Can address memory in 16-bit words
Conclusion: The 16-bit ALU is the determining factor, supported by 16-bit registers and data bus
ALU Operations in Detail
Arithmetic Operations
| Operation | Description | Data Types | Flags Affected | Example |
|---|
| Addition | ADD two operands | 8-bit, 16-bit | CF, PF, AF, ZF, SF, OF | ADD AX, BX |
| Subtraction | SUB second from first | 8-bit, 16-bit | CF, PF, AF, ZF, SF, OF | SUB AX, 100H |
| Multiplication | MUL unsigned operands | 8×8=16, 16×16=32 | CF, OF (others undefined) | MUL BL |
| Division | DIV unsigned operands | 16÷8, 32÷16 | All flags undefined | DIV CL |
Logical Operations
| Operation | Description | Truth Function | Common Use |
|---|
| AND | Bitwise AND operation | 1 & 1 = 1, others = 0 | Bit masking, clearing bits |
| OR | Bitwise OR operation | 0 | 0 = 0, others = 1 | Bit setting, combining bits |
| XOR | Bitwise exclusive OR | Same bits = 0, different = 1 | Bit toggling, encryption |
| NOT | Bitwise complement | 0 becomes 1, 1 becomes 0 | Bit inversion, 1's complement |
ALU Integration with Other Components
The ALU doesn't operate in isolation but works closely with other processor components:
- Registers: Provide operands and store results
- Flag Register: Stores operation status and conditions
- Control Unit: Decodes instructions and controls ALU operations
- Internal Bus: Transfers data to/from ALU
- Instruction Queue: Provides operation codes to control unit
Control Bus - System Coordination and Communication
The control bus is a collection of signal lines that coordinate and control all data transfer operations within the computer system. Unlike address and data buses, the control bus is not a simple parallel bus but consists of individual control lines, each carrying specific control information.
Control Bus Functions and Importance
The control bus serves several critical functions in system operation:
- Operation Control: Specifies whether CPU wants to read or write
- Device Selection: Indicates whether operation targets memory or I/O
- Timing Coordination: Synchronizes operations across system components
- System Status: Provides status information about CPU state
- Interrupt Handling: Manages interrupt requests and acknowledgments
- Bus Arbitration: Controls access to shared system buses
Essential Control Signals in 8086
| Signal | Full Name | Direction | Function | Active State |
|---|
| RD | Read (active low) | Output | Indicates CPU wants to read data from memory/I/O | Active LOW (0) |
| WR | Write (active low) | Output | Indicates CPU wants to write data to memory/I/O | Active LOW (0) |
| M/IO | Memory/IO (active low IO) | Output | Distinguishes memory (1) vs I/O (0) operation | HIGH=Memory, LOW=I/O |
| ALE | Address Latch Enable | Output | Latches address from multiplexed AD bus | Active HIGH (1) |
| DEN | Data Enable (active low) | Output | Enables data bus transceivers | Active LOW (0) |
| DT/R | Data Transmit/Receive | Output | Controls data bus direction (1=transmit, 0=receive) | HIGH=Transmit, LOW=Receive |
| READY | Ready | Input | Indicates memory/I/O device is ready for transfer | Active HIGH (1) |
| INTR | Interrupt Request | Input | Maskable interrupt request from external device | Active HIGH (1) |
| NMI | Non-Maskable Interrupt | Input | Non-maskable interrupt (highest priority) | Rising Edge Triggered |
| RESET | Reset | Input | Resets the processor to initial state | Active HIGH (1) |
Control Signal Timing and Coordination
The control signals work together in specific sequences during different bus cycles:
Memory Read Cycle Sequence:
- ALE goes HIGH: Address is valid on AD bus
- ALE goes LOW: Address is latched externally
- M/IO goes HIGH: Indicates memory operation
- RD goes LOW: Initiates read operation
- DEN goes LOW: Enables data bus receivers
- DT/R goes LOW: Sets data bus for receiving
- READY checked: Waits for memory ready signal
- Data latched: CPU reads data from bus
- RD goes HIGH: Terminates read cycle
Memory Write Cycle Sequence:
- ALE goes HIGH: Address is valid on AD bus
- ALE goes LOW: Address is latched externally
- M/IO goes HIGH: Indicates memory operation
- DT/R goes HIGH: Sets data bus for transmitting
- DEN goes LOW: Enables data bus drivers
- Data placed: CPU places data on bus
- WR goes LOW: Initiates write operation
- READY checked: Waits for memory ready signal
- WR goes HIGH: Terminates write cycle
Bus Control vs Address/Data Buses
| Aspect | Address Bus | Data Bus | Control Bus |
|---|
| Direction | Unidirectional (CPU to Memory) | Bidirectional | Mixed (both input and output lines) |
| Width | Fixed (20 bits) | Fixed (16 bits) | Variable (multiple individual signals) |
| Function | Carries location information | Carries actual data | Carries control and status information |
| Signal Type | Parallel digital signals | Parallel digital signals | Individual control lines |
Memory and Data Storage Organization
Understanding how the 8086 organizes and accesses memory is crucial for programming and system design. The 8086 uses a linear memory model with specific rules for data storage and retrieval.
8086 Memory Organization
- Total Memory Size: 1 MB (1,048,576 bytes)
- Address Range: 00000H to FFFFFH
- Organization: Linear addressing with segmentation
- Access: Byte-addressable memory
Key Memory Rules
Fundamental Memory Rule:
One memory location stores exactly one byte (8 bits) of data
Storing 16-bit Data in Memory
Since each memory location stores only 1 byte, 16-bit data requires 2 consecutive memory locations:
Example: Storing 16-bit data 1234H
| Address | Data (Hex) | Description |
|---|
| 1000H | 34H | Lower byte (LSB) |
| 1001H | 12H | Higher byte (MSB) |
Little Endian Format in 8086
Little Endian Format in 8086:
"Lower byte is stored at the lower address"
For 16-bit data ABCDH:
- Lower byte (CDH) → Stored at lower address
- Higher byte (ABH) → Stored at higher address
Little Endian Examples:
Example 1: Data = 5678H, Starting Address = 2000H
| Address | Data | Byte Type |
|---|
| 2000H | 78H | Lower byte (LSB) |
| 2001H | 56H | Higher byte (MSB) |
Example 2: Data = 9ABCH, Starting Address = 3000H
| Address | Data | Byte Type |
|---|
| 3000H | BCH | Lower byte (LSB) |
| 3001H | 9AH | Higher byte (MSB) |
Memory Structure and System Organization
The 8086 memory is organized as a linear array of bytes, each with a unique 20-bit address.
Memory Map Overview
| Address Range | Size | Typical Usage | Description |
|---|
| 00000H - 003FFH | 1 KB | Interrupt Vector Table | 256 interrupt vectors (4 bytes each) |
| 00400H - 9FFFFH | ~640 KB | User RAM | Available for user programs |
| A0000H - BFFFFH | 128 KB | Video Memory | Graphics and text display memory |
| C0000H - FFFFFH | 256 KB | System ROM | BIOS and system firmware |
Memory Access Examples
Memory Read Operation Example:
Task: Read 16-bit data from address 5000H
- CPU places 5000H on address bus
- Sets M/IO̱ = 1, READ̄ = 0 (Memory Read)
- Memory returns byte at 5000H (lower byte)
- CPU places 5001H on address bus
- Memory returns byte at 5001H (higher byte)
- CPU combines both bytes using Little Endian format
Practical Examples and Calculations
Address Bus Calculation Problems
Problem 1:
Question: A processor has a 22-bit address bus. Calculate the maximum memory it can address.
Solution:
- Address Bus = 22 bits
- Maximum Memory = 2^22 = 4,194,304 bytes
- = 4,194,304 bytes = 4096 KB = 4 MB
- Address Range: 000000H to 3FFFFFH
Problem 2:
Question: Store the 16-bit number 7A5BH starting at memory address 8000H using Little Endian format.
Solution:
| Address | Data Stored | Explanation |
|---|
| 8000H | 5BH | Lower byte at lower address |
| 8001H | 7AH | Higher byte at higher address |
Data Transfer Speed Comparison
Transferring 1000 bytes of data:
- 8085 (8-bit data bus): 1000 memory accesses required
- 8086 (16-bit data bus): 500 memory accesses required
- Performance gain: 8086 is 2x faster for bulk data transfer
Summary and Key Takeaways
Essential Points to Remember:
- Address Bus (20-bit): Determines maximum memory = 1 MB
- Data Bus (16-bit): Determines transfer speed and word size
- Control Bus: Coordinates all operations with READ̄, WRITĒ, M/IO̱
- ALU (16-bit): Makes 8086 a true 16-bit processor
- 8086 vs 8088: Same internally, different data bus externally
- Memory Rule: One location = One byte
- Little Endian: Lower byte at lower address
Next Topics to Explore
Now that you understand the fundamentals, explore these advanced topics:
- 8086 Architecture: Internal structure and organization
- Addressing Modes: Different ways to specify operands
- Instruction Set: Complete command reference
- Assembly Programming: Writing programs in assembly language
