8086 Numerical Problems and Solutions
Master 8086 microprocessor concepts through comprehensive numerical problems covering addressing modes, memory management, timing calculations, and programming challenges with detailed step-by-step solutions.
Category 1: Address Calculation Problems
Problem 1.1: Physical Address Calculation
Question: Calculate the physical address when CS = 2000H and IP = 1500H.
Solution:
Given:
CS (Code Segment) = 2000H
IP (Instruction Pointer) = 1500H
Physical Address = (CS × 16) + IP
= (2000H × 16) + 1500H
= 20000H + 1500H
= 21500H
Answer: Physical Address = 21500H
Problem 1.2: Data Segment Addressing
Question: If DS = 3000H and offset = 2500H, find the physical address and determine the maximum offset possible.
Solution:
Part A: Physical Address Calculation
DS = 3000H, Offset = 2500H
Physical Address = (DS × 16) + Offset
= (3000H × 16) + 2500H
= 30000H + 2500H
= 32500H
Part B: Maximum Offset
Maximum offset in 8086 = FFFFH (65535 decimal)
Maximum Physical Address = 30000H + FFFFH = 3FFFFH
Answer: Physical Address = 32500H, Max Offset = FFFFH
Problem 1.3: Overlapping Segments
Question: Given CS = 1200H and DS = 1000H, find the overlapping memory range.
Solution:
CS = 1200H:
Start Address = 1200H × 16 = 12000H
End Address = 12000H + FFFFH = 21FFFH
DS = 1000H:
Start Address = 1000H × 16 = 10000H
End Address = 10000H + FFFFH = 1FFFFH
Overlapping Range:
Start = MAX(12000H, 10000H) = 12000H
End = MIN(21FFFH, 1FFFFH) = 1FFFFH
Overlap Size = 1FFFFH - 12000H + 1 = E000H bytes (57344 decimal)
Answer: Overlapping range is 12000H to 1FFFFH
Category 2: Memory Management Problems
Problem 2.1: Memory Segmentation
Question: A program needs 40KB of memory. How should it be distributed among segments?
Solution:
Given: Total memory needed = 40KB = 40960 bytes
Each segment maximum size = 64KB = 65536 bytes
Since 40KB < 64KB, it can fit in one segment
Recommended Distribution:
- Code Segment (CS): 16KB (for program instructions)
- Data Segment (DS): 16KB (for variables and data)
- Stack Segment (SS): 4KB (for stack operations)
- Extra Segment (ES): 4KB (for additional data/string operations)
Total: 16 + 16 + 4 + 4 = 40KB
Answer: Use single segment or distribute as shown above
Problem 2.2: Stack Pointer Calculation
Question: If SS = 2000H and SP = 1000H, what happens after PUSH AX and POP BX operations?
Solution:
Initial Conditions:
SS = 2000H, SP = 1000H
Stack Physical Address = (2000H × 16) + 1000H = 21000H
After PUSH AX:
1. SP decrements by 2: SP = 1000H - 2 = 0FFEH
2. AX contents stored at (SS × 16) + SP = 20000H + 0FFEH = 20FFEH
3. New stack top at physical address 20FFEH
After POP BX:
1. Data from (SS × 16) + SP loaded into BX
2. BX = contents from 20FFEH (previously stored AX value)
3. SP increments by 2: SP = 0FFEH + 2 = 1000H
Final State: SP = 1000H (back to original), BX = original AX value
Answer: Stack returns to original state, BX contains original AX value
Problem 2.3: Memory Bank Selection
Question: In 8086 system with 1MB memory, calculate the number of memory banks needed for word operations.
Solution:
8086 Memory Organization:
- Total addressable memory = 1MB = 1048576 bytes
- Data bus width = 16 bits = 2 bytes
- Memory is organized in two banks: even and odd
Bank Organization:
- Even Bank: Addresses ending in 0 (A0 = 0)
- Odd Bank: Addresses ending in 1 (A0 = 1)
Each bank size = 1MB ÷ 2 = 512KB = 524288 bytes
For word operations:
- Word at even address: uses both banks simultaneously
- Word at odd address: requires two bus cycles
- BHE (Bus High Enable) controls odd bank access
Answer: 2 memory banks of 512KB each are needed
Category 3: Timing and Performance Problems
Problem 3.1: Instruction Execution Time
Question: Calculate total execution time for the following program running at 8MHz:
MOV AX, 1234H ; 4 clock cycles
ADD AX, BX ; 3 clock cycles
MOV [SI], AX ; 9 clock cycles
INC SI ; 2 clock cycles
Solution:
Given: Clock frequency = 8MHz
Clock period = 1/8MHz = 0.125 µs = 125 ns
Instruction Analysis:
MOV AX, 1234H : 4 cycles × 125 ns = 500 ns
ADD AX, BX : 3 cycles × 125 ns = 375 ns
MOV [SI], AX : 9 cycles × 125 ns = 1125 ns
INC SI : 2 cycles × 125 ns = 250 ns
Total clock cycles = 4 + 3 + 9 + 2 = 18 cycles
Total execution time = 18 × 125 ns = 2250 ns = 2.25 µs
Answer: Total execution time = 2.25 microseconds
Problem 3.2: Memory Access Time Analysis
Question: A memory chip has 200ns access time. How many wait states are needed for 10MHz 8086?
Solution:
Given:
- Memory access time = 200 ns
- CPU frequency = 10 MHz
- Clock period = 1/10MHz = 100 ns
Memory Read Cycle Analysis:
T1: Address setup (100 ns)
T2: RD signal assertion (100 ns)
T3: Data read time (100 ns)
T4: Data hold time (100 ns)
Available time for memory access = T2 + T3 = 200 ns
Required time by memory = 200 ns
Since available time = required time, no wait states needed.
Verification:
If wait states were needed:
Required wait states = ⌈(200 - 200)/100⌉ = 0
Answer: 0 wait states needed
Problem 3.3: System Throughput Calculation
Question: Compare throughput of 5MHz vs 8MHz 8086 for a loop with 1000 iterations, each taking 20 clock cycles.
Solution:
Loop Analysis:
Total clock cycles = 1000 iterations × 20 cycles = 20,000 cycles
For 5MHz System:
Clock period = 1/5MHz = 200 ns
Total time = 20,000 × 200 ns = 4,000,000 ns = 4 ms
For 8MHz System:
Clock period = 1/8MHz = 125 ns
Total time = 20,000 × 125 ns = 2,500,000 ns = 2.5 ms
Performance Comparison:
Speedup = 4 ms / 2.5 ms = 1.6×
Throughput ratio = 8MHz / 5MHz = 1.6×
Answer: 8MHz system is 1.6× faster, completing in 2.5ms vs 4ms
Category 4: Data Conversion Problems
Problem 4.1: Number System Conversions
Question: Convert the following values for 8086 operations:
- Decimal 1234 to hexadecimal
- Binary 1101110110101 to hexadecimal
- Hexadecimal 4A3CH to decimal
Solution:
Part A: Decimal 1234 to Hexadecimal
1234 ÷ 16 = 77 remainder 2
77 ÷ 16 = 4 remainder 13 (D)
4 ÷ 16 = 0 remainder 4
Reading remainders upward: 4D2H
Part B: Binary 1101110110101 to Hexadecimal
Group into 4-bit chunks from right:
1 1011 1011 0101
0001 1011 1011 0101
1 B B 5
Result: 1BB5H
Part C: Hexadecimal 4A3CH to Decimal
4A3CH = 4×16³ + A×16² + 3×16¹ + C×16⁰
= 4×4096 + 10×256 + 3×16 + 12×1
= 16384 + 2560 + 48 + 12
= 19004 decimal
Answer: 1234₁₀ = 4D2H, 1101110110101₂ = 1BB5H, 4A3CH = 19004₁₀
Problem 4.2: Signed Number Representation
Question: Represent -1234 in 16-bit two's complement form and verify the result.
Solution:
Step 1: Convert 1234 to binary
1234 = 0000010011010010₂ (16-bit)
Step 2: Find one's complement
One's complement = 1111101100101101₂
Step 3: Add 1 for two's complement
1111101100101101
+ 1
________________
1111101100101110₂
Step 4: Convert to hexadecimal
1111 1011 0010 1110 = FB2EH
Verification:
FB2EH = -1234 in two's complement
To verify: take two's complement of FB2EH should give 1234
One's complement of FB2E = 04D1
04D1 + 1 = 04D2H = 1234₁₀ (Correct)
Answer: -1234 in 16-bit two's complement = FB2EH
Category 5: Programming Logic Problems
Problem 5.1: Loop Optimization
Question: Calculate the overhead for different loop implementations to add 100 numbers.
Solution:
Method 1: Using LOOP instruction
MOV CX, 100 ; 4 cycles, once
AGAIN:
ADD AX, [SI] ; 9 cycles, 100 times
INC SI ; 2 cycles, 100 times
INC SI ; 2 cycles, 100 times (for word data)
LOOP AGAIN ; 17 cycles, 100 times
Total cycles = 4 + 100×(9+2+2+17) = 4 + 100×30 = 3004 cycles
Method 2: Using DEC/JNZ
MOV CX, 100 ; 4 cycles, once
AGAIN:
ADD AX, [SI] ; 9 cycles, 100 times
ADD SI, 2 ; 4 cycles, 100 times
DEC CX ; 2 cycles, 100 times
JNZ AGAIN ; 16 cycles, 99 times; 4 cycles, 1 time
Total cycles = 4 + 100×(9+4+2) + 99×16 + 1×4 = 4 + 1500 + 1584 + 4 = 3092 cycles
Answer: LOOP instruction is more efficient (3004 vs 3092 cycles)
Problem 5.2: String Operation Efficiency
Question: Compare the performance of manual loop vs REP MOVSW for copying 1000 words.
Solution:
Method 1: Manual Loop
MOV CX, 1000 ; 4 cycles
AGAIN:
MOV AX, [SI] ; 8 cycles × 1000
MOV [DI], AX ; 9 cycles × 1000
ADD SI, 2 ; 4 cycles × 1000
ADD DI, 2 ; 4 cycles × 1000
LOOP AGAIN ; 17 cycles × 1000
Total = 4 + 1000×(8+9+4+4+17) = 4 + 42000 = 42004 cycles
Method 2: REP MOVSW
MOV CX, 1000 ; 4 cycles
REP MOVSW ; 9 cycles setup + 17 cycles × 1000
Total = 4 + 9 + 17000 = 17013 cycles
Efficiency Gain:
Speedup = 42004/17013 = 2.47×
Time saved = (42004-17013)/42004 = 59.5%
Answer: REP MOVSW is 2.47× faster than manual loop
Category 6: I/O and Interrupt Problems
Problem 6.1: I/O Port Address Decoding
Question: Design address decoding for I/O ports at addresses 300H-303H. How many address lines are needed?
Solution:
Given I/O addresses: 300H, 301H, 302H, 303H
Step 1: Convert to binary
300H = 0011 0000 0000₂
301H = 0011 0000 0001₂
302H = 0011 0000 0010₂
303H = 0011 0000 0011₂
Step 2: Identify common bits
Common bits: 0011 0000 00XX
A9-A2 = 11000000₂ for base address decoding
A1-A0 = XX for port selection within the range
Step 3: Address lines needed
- A9-A2 for range decoding: requires 8-input decoder
- A1-A0 for port selection: requires 2-4 decoder
- Total address lines used: A0-A9 (10 lines)
Step 4: Decoder logic
Enable when A9-A2 = 11000000₂ and IO/M = 1
Port selection: A1A0 = 00(300H), 01(301H), 10(302H), 11(303H)
Answer: 10 address lines needed with proper decoding logic
Problem 6.2: Interrupt Priority Calculation
Question: Calculate interrupt vector addresses for interrupts 20H, 21H, and 25H.
Solution:
Interrupt Vector Table (IVT) Calculation:
Each interrupt vector = 4 bytes (2 bytes IP + 2 bytes CS)
Vector address = Interrupt number × 4
For Interrupt 20H:
Vector address = 20H × 4 = 80H
IP stored at: 0000:0080H
CS stored at: 0000:0082H
For Interrupt 21H:
Vector address = 21H × 4 = 84H
IP stored at: 0000:0084H
CS stored at: 0000:0086H
For Interrupt 25H:
Vector address = 25H × 4 = 94H
IP stored at: 0000:0094H
CS stored at: 0000:0096H
Memory Layout:
0080H: IP(low) of INT 20H
0081H: IP(high) of INT 20H
0082H: CS(low) of INT 20H
0083H: CS(high) of INT 20H
...and so on
Answer: INT 20H→80H, INT 21H→84H, INT 25H→94H
Category 7: Advanced Problems
Problem 7.1: Memory Mapping and Decoding
Question: Design memory map for a system with 32KB ROM at F8000H and 32KB RAM at 40000H. Calculate the required decoder logic.
Solution:
Given:
- ROM: 32KB at F8000H
- RAM: 32KB at 40000H
- 32KB = 8000H bytes
ROM Address Range:
Start: F8000H = 1111 1000 0000 0000 0000₂
End: F8000H + 7FFFH = FFFFFH
RAM Address Range:
Start: 40000H = 0100 0000 0000 0000 0000₂
End: 40000H + 7FFFH = 47FFFH
Decoder Logic:
For ROM (F8000H-FFFFFH):
A19 A18 A17 A16 A15 = 11111 (to enable ROM)
For RAM (40000H-47FFFH):
A19 A18 A17 A16 A15 = 01000 (to enable RAM)
Address Lines Used:
- A19-A15: Device selection (ROM vs RAM vs other)
- A14-A0: Address within device (32K addressing)
Decoder Implementation:
ROM_CS = A19 · A18 · A17 · A16 · A15
RAM_CS = A19' · A18 · A17' · A16' · A15'
Answer: Use 5-input decoders for A19-A15 to select devices
Problem 7.2: Performance Optimization Analysis
Question: A program has 40% arithmetic, 30% memory access, and 30% branch instructions. Calculate overall performance improvement if arithmetic speed doubles.
Solution:
Given:
- Arithmetic instructions: 40% of total time
- Memory access: 30% of total time
- Branch instructions: 30% of total time
- Arithmetic speed improvement: 2× (50% faster)
Using Amdahl's Law:
Speedup = 1 / ((1-P) + P/S)
Where P = fraction improved, S = speedup factor
P = 0.4 (40% arithmetic instructions)
S = 2 (arithmetic is 2× faster)
Overall Speedup = 1 / ((1-0.4) + 0.4/2)
= 1 / (0.6 + 0.2)
= 1 / 0.8
= 1.25
Performance Analysis:
- Original time: 100 units
- New time: 100/1.25 = 80 units
- Time saved: 20 units (20% improvement)
Answer: Overall system performance improves by 25%
Practice Problem Set
Quick Problems for Self-Assessment
Problem Set A: Basic Calculations
- Calculate physical address when DS=4000H, SI=1200H
- Convert 2AC5H to decimal
- Find two's complement of 1000H
- Calculate execution time for 50 cycles at 6MHz
Problem Set B: Intermediate Problems
- Design I/O decoding for ports 200H-20FH
- Calculate stack usage for 5 nested CALL instructions
- Determine memory bandwidth for 8MHz system
- Find interrupt vector for software interrupt 30H
Problem Set C: Advanced Challenges
- Optimize bubble sort for 100 elements
- Design memory mapping for 1MB system
- Calculate performance impact of cache misses
- Analyze real-time system timing constraints
Problem-Solving Strategies
1. Address Calculation Strategy
Always remember: Physical Address = (Segment × 16) + Offset
2. Timing Analysis Approach
Break down into: Clock cycles → Clock period → Total time
3. Memory Design Method
Identify: Address range → Decoder logic → Enable signals
4. Performance Optimization
Focus on: Instruction selection → Loop efficiency → Memory access patterns
5. Number System Conversions
Use systematic approach: Division method for base conversion
Summary and Key Formulas
Essential Formulas:
Physical Address = (Segment × 16) + Offset
Execution Time = Clock Cycles × Clock Period
Clock Period = 1 / Clock Frequency
Memory Size = End Address - Start Address + 1
Two's Complement = One's Complement + 1
Interrupt Vector Address = Interrupt Number × 4
Speedup = Original Time / New Time
Efficiency = (Time Saved / Original Time) × 100%
Common Values to Remember:
- Maximum segment size: 64KB (10000H bytes)
- Maximum offset: FFFFH (65535 decimal)
- Total addressable memory: 1MB (100000H)
- Interrupt vector size: 4 bytes each
- Word size: 2 bytes (16 bits)
- Address bus width: 20 bits
- Data bus width: 16 bits
