8086 Clock Generation and Timing

Clock System Overview

The 8086 microprocessor requires an external clock signal to coordinate all internal operations. The clock frequency determines the speed of instruction execution and overall system performance.

Clock Specifications:

• Clock Input: Pin 19 (CLK)
• Frequency Range: 5-10 MHz (standard versions)
• Duty Cycle: 33% minimum high time
• Logic Levels: TTL compatible (0V-0.8V low, 2.0V-5V high)

Machine Cycle Fundamentals

A machine cycle is the basic unit of time required to perform a fundamental operation. The 8086 machine cycle consists of a minimum of 4 clock periods called T-states.

T-States (Clock Periods):

• T1: Address/Status Output
• T2: Address Hold/Data Setup
• T3: Data Transfer
• T4: Data Hold/Cleanup
• TW: Wait State (if READY is low)

Read Machine Cycle Timing

The read cycle is used to fetch instructions or read data from memory or I/O ports.

Read Cycle Steps:

T1: - Address (A19-A0) is output
    - ALE goes high to latch address
    - IO/M, DT/R signals are set

T2: - Address is latched externally
    - ALE goes low
    - RD signal goes low
    - Data bus floats

T3: - Data is read from memory/IO
    - DEN enables data transceivers
    - Data setup time must be met

T4: - Data is latched into CPU
    - RD signal goes high
    - Bus is prepared for next cycle

Write Machine Cycle Timing

The write cycle is used to write data to memory or I/O ports.

Write Cycle Steps:

T1: - Address (A19-A0) is output
    - ALE goes high
    - IO/M signal is set
    - DT/R = 1 (transmit mode)

T2: - Address is latched
    - ALE goes low
    - Data is output on bus
    - WR signal preparation

T3: - WR signal goes low
    - Data is valid on bus
    - Memory/IO device writes data

T4: - WR signal goes high
    - Data hold time maintained
    - Cycle completion

Timing Differences:

• Read Cycle: CPU inputs data from external device
• Write Cycle: CPU outputs data to external device
• Signal Timing: RD/WR signals have different timing requirements

Instruction Execution Timing

Different instructions require different numbers of machine cycles and clock periods for execution.

Instruction Categories:

Register Operations:    2-4 clock cycles
Memory Operations:      8-16 clock cycles
I/O Operations:         10-16 clock cycles
Branch Instructions:    4-16 clock cycles
Multiply/Divide:        118-190 clock cycles

Examples:

Instruction          | Clock Cycles | Machine Cycles
MOV AX, BX          |      2       |       1
MOV AX, [1234H]     |      8       |       2
ADD AX, [BX]        |     9+EA     |      2+
MUL BX              |   70-77      |     17-19
JMP SHORT label     |     15       |       3
CALL near proc      |     19       |       4

Wait States and READY Signal

The READY signal allows slower memory or I/O devices to extend machine cycles by inserting wait states.

READY Signal Operation:

READY = 1: Normal operation, no wait states
READY = 0: Insert wait state (TW)

During TW state:
- Current T-state is extended
- Address and control signals remain stable
- CPU waits for READY to go high
- Multiple wait states possible

Wait State Calculation:

If a memory device requires 200ns access time and CPU clock is 8MHz (125ns period):

Required time: 200ns
Clock period: 125ns
Wait states needed: 200ns / 125ns = 1.6 ≈ 2 wait states
Total cycle time: 4 + 2 = 6 clock periods

Bus Timing and Address Latch Enable (ALE)

ALE signal is crucial for demultiplexing address and data on the shared AD0-AD15 pins.

ALE Timing:

T1 State:
- ALE goes HIGH at start of T1
- Address is valid on AD0-AD15
- External latch (74LS373) is transparent

T1 to T2 Transition:
- ALE goes LOW
- Address is latched in external latch
- AD0-AD15 pins switch to data mode

T2-T4 States:
- ALE remains LOW
- AD0-AD15 carry data signals
- Latched address remains stable

ALE Frequency:

ALE frequency = Clock frequency / 4 (since ALE pulses once per machine cycle)

Numerical Problems and Solutions

Problem 1: Execution Time Calculation

Question: Calculate the execution time for MOV AX, [1234H] instruction if 8086 operates at 8MHz.

Solution:

Given:
- Clock frequency = 8MHz
- MOV AX, [memory] requires 8 clock cycles

Step 1: Calculate clock period
Clock period = 1/8MHz = 0.125 µs = 125 ns

Step 2: Calculate execution time
Execution time = Clock cycles × Clock period
               = 8 × 125 ns = 1000 ns = 1 µs

Problem 2: Memory Access Time

Question: A memory chip has 150ns access time. How many wait states are needed for 5MHz 8086?

Solution:

Given:
- Memory access time = 150 ns
- Clock frequency = 5MHz
- Clock period = 1/5MHz = 200 ns

Step 1: Normal read cycle timing
T1: 200 ns (address setup)
T2: 200 ns (RD signal low)
T3: 200 ns (data read)
Available time for memory = T2 + T3 = 400 ns

Step 2: Check if wait states needed
Required time: 150 ns
Available time: 400 ns
Since 150 ns < 400 ns, NO wait states needed

Problem 3: ALE Frequency Calculation

Question: If 8086 operates at 10MHz, what is the ALE frequency and period?

Solution:

Given: Clock frequency = 10 MHz

Step 1: ALE frequency calculation
ALE frequency = Clock frequency / 4
              = 10 MHz / 4 = 2.5 MHz

Step 2: ALE period calculation
ALE period = 1 / ALE frequency
           = 1 / 2.5 MHz = 0.4 µs = 400 ns

This means ALE pulses every 400 ns (every machine cycle)

Problem 4: Instruction Throughput

Question: Calculate instructions per second for simple register operations at 8MHz.

Solution:

Given:
- Clock frequency = 8 MHz
- Simple register instruction = 2 clock cycles

Step 1: Time per instruction
Time per instruction = 2 × (1/8MHz) = 2 × 125 ns = 250 ns

Step 2: Instructions per second
Instructions per second = 1 / 250 ns
                        = 1 / (250 × 10⁻⁹)
                        = 4 × 10⁶ = 4 MIPS

Problem 5: System Performance

Question: Compare performance of 5MHz vs 10MHz 8086 for the same program.

Solution:

Performance ratio = Higher frequency / Lower frequency
                  = 10 MHz / 5 MHz = 2

Therefore:
- 10MHz system is 2× faster than 5MHz system
- Same program takes half the time on 10MHz system
- Instruction execution rate doubles

Timing Optimization Techniques

1. Minimize Memory Access

Use registers instead of memory variables when possible to reduce clock cycles.

2. Instruction Selection

Choose faster instruction variants:

Slower: MOV AX, 0     (3 cycles)
Faster: XOR AX, AX    (2 cycles)

Slower: MOV [BX], 0   (10 cycles)
Faster: AND [BX], 0   (16 cycles) - Actually slower!
        Use: MOV AL, 0; MOV [BX], AL (9 cycles)

3. Memory Organization

Organize data to minimize effective address calculations.

Common Timing Issues and Solutions

1. Setup and Hold Time Violations

Problem: Data not stable when required

Solution: Add wait states or use faster memory

2. Clock Skew

Problem: Clock signal arrives at different times

Solution: Proper PCB layout and clock distribution

3. Metastability

Problem: Asynchronous signals violate setup/hold times

Solution: Synchronizer circuits with multiple flip-flops

Practical Applications

1. Real-Time Systems

Understanding timing is crucial for meeting real-time deadlines in embedded systems.

2. Performance Analysis

Calculate program execution times for system optimization.

3. Hardware Design

Design memory and I/O interfaces with proper timing margins.

4. Debugging

Timing diagrams help identify and fix hardware timing issues.

Summary

Clock generation and timing are fundamental to 8086 operation. Understanding machine cycles, instruction timing, and bus timing is essential for system design, performance optimization, and debugging. Proper timing ensures reliable operation and maximum system performance.

Key Points:

• Machine cycle consists of minimum 4 T-states
• Different instructions require different clock cycles
• READY signal can insert wait states for slow devices
• ALE signal enables address/data demultiplexing
• Timing analysis is crucial for performance optimization
• Setup and hold times must be respected for reliable operation