8086 Buses and Memory Architecture
Master the bus structure and memory organization of 8086 microprocessor with detailed explanations, practical examples, and numerical problems.
Bus System Overview and Architecture
The 8086 microprocessor communicates with external components through three distinct bus systems, each serving a specific purpose in data transfer and system coordination.
Complete Bus Specification
| Bus Type | Width (bits) | Function | Direction | Key Characteristics |
|---|
| Address Bus | 20 | Specify memory/I/O location | Unidirectional (CPU → Memory) | Determines addressable space |
| Data Bus | 16 | Transfer data/instructions | Bidirectional (CPU ↔ Memory) | Determines transfer rate |
| Control Bus | Variable | Coordinate operations | Unidirectional (CPU → System) | Manages timing and control |
Address Bus - Memory Addressing Foundation
The 20-bit address bus is the foundation of 8086's memory addressing capability, determining the maximum memory space accessible to the processor.
Address Bus Calculation Fundamentals
8086 Address Bus Analysis
Step-by-Step Calculation:
- Given: Address Bus = 20 bits
- Maximum Addresses: 2^20 = 1,048,576
- Memory Size: 1,048,576 bytes = 1 MB
- Address Range: 00000H to FFFFFH
- Hexadecimal Range: 0 to 1,048,575 (decimal)
Comparative Analysis - Address Bus Sizes
| Address Bus (bits) | Maximum Addresses | Memory Size | Address Range (Hex) | Example Processors |
|---|
| 8 | 256 | 256 B | 00H - FFH | Simple microcontrollers |
| 12 | 4,096 | 4 KB | 000H - FFFH | Early microprocessors |
| 16 | 65,536 | 64 KB | 0000H - FFFFH | 8085, Z80 |
| 20 | 1,048,576 | 1 MB | 00000H - FFFFFH | 8086, 8088 |
| 24 | 16,777,216 | 16 MB | 000000H - FFFFFFH | 80286 |
| 32 | 4,294,967,296 | 4 GB | 00000000H - FFFFFFFFH | 80386, 80486 |
Practical Address Bus Problems
Problem 1: Custom Address Bus
Question: A processor has an 18-bit address bus. Calculate:
- Maximum memory addressable
- Address range in hexadecimal
- Memory size in KB and MB
Solution:
- Maximum Memory = 2^18 = 262,144 bytes
- Address Range: 00000H to 3FFFFH
- Memory Size: 256 KB = 0.25 MB
Problem 2: Required Address Bus
Question: How many address lines are needed to address 8 MB of memory?
Solution:
- Required Memory = 8 MB = 8 × 1024 × 1024 = 8,388,608 bytes
- 2^n ≥ 8,388,608
- 2^23 = 8,388,608
- Answer: 23 address lines required
Data Bus - Information Transfer Highway
The 16-bit data bus determines how much information can be transferred between the CPU and memory/I/O devices in a single operation.
Data Bus Impact on System Performance
8086 vs 8088 - The Critical Difference
| Feature | 8086 | 8088 | Impact |
|---|
| External Data Bus | 16 bits | 8 bits | 2x speed difference |
| Internal Architecture | 16 bits | 16 bits | Same processing power |
| Memory Interface | 16-bit wide | 8-bit wide | Cost vs performance |
| 16-bit Data Fetch | 1 memory cycle | 2 memory cycles | 50% speed penalty |
| Cost | Higher | Lower | Market positioning |
| Pin Count | 40 pins | 40 pins | Same package |
Data Transfer Performance Examples
Example 1: Transferring 1000 bytes
| Processor | Data Bus | Memory Accesses | Time (relative) |
|---|
| 8085 | 8 bits | 1000 | 100% |
| 8088 | 8 bits | 1000 | 100% |
| 8086 | 16 bits | 500 | 50% |
Example 2: Reading 16-bit instruction
- 8086: Single memory read → Faster execution
- 8088: Two memory reads → Slower execution
- Performance impact: 8086 is approximately 30-40% faster overall
Control Bus - System Coordination
The control bus carries various control signals that coordinate and synchronize all data transfer operations in the 8086 system.
Essential Control Signals
| Signal Name | Symbol | Function | Active State | Source |
|---|
| Read | READ̄ or RD̄ | Indicates CPU wants to read data | Active LOW (0) | CPU Output |
| Write | WRITĒ or WR̄ | Indicates CPU wants to write data | Active LOW (0) | CPU Output |
| Memory/IO | M/IO̱ | Selects memory or I/O operation | HIGH=Memory, LOW=I/O | CPU Output |
| Address Latch Enable | ALE | Latches address from multiplexed bus | Active HIGH (1) | CPU Output |
| Data Transmit/Receive | DT/R̄ | Controls data bus direction | HIGH=Transmit, LOW=Receive | CPU Output |
Four Basic Operations
Control signals combine to create four fundamental data transfer operations:
| Operation | M/IO̱ | READ̄ | WRITĒ | Description | Example |
|---|
| Memory Read | 1 | 0 | 1 | CPU reads from memory | Fetch instruction |
| Memory Write | 1 | 1 | 0 | CPU writes to memory | Store data |
| I/O Read | 0 | 0 | 1 | CPU reads from I/O port | Read keyboard |
| I/O Write | 0 | 1 | 0 | CPU writes to I/O port | Send to printer |
Control Signal Timing
Typical Memory Read Cycle:
- CPU places address on address bus
- ALE goes HIGH to latch address
- M/IO̱ = 1 (memory operation)
- READ̄ = 0 (read operation)
- Memory places data on data bus
- CPU reads data
- READ̄ = 1 (end of cycle)
Memory Organization and Data Storage
Understanding how 8086 organizes memory and stores data is crucial for effective programming and system design.
Memory Organization Hierarchy
| Level | Address Range | Size | Typical Usage | Access Speed |
|---|
| Interrupt Vectors | 00000H - 003FFH | 1 KB | Interrupt service routines | Fast |
| System RAM | 00400H - 9FFFFH | 640 KB | User programs and data | Medium |
| Video Memory | A0000H - BFFFFH | 128 KB | Display buffer | Fast |
| Extended ROM | C0000H - EFFFFH | 192 KB | Adapter ROMs | Slow |
| System ROM | F0000H - FFFFFH | 64 KB | BIOS and bootstrap | Slow |
Fundamental Memory Rules
Rule 1: Memory Cell Size
One memory location stores exactly one byte (8 bits) of data
- Smallest addressable unit = 1 byte
- Each address points to 1 byte
- Larger data requires multiple locations
Rule 2: Sequential Addressing
Consecutive memory locations have consecutive addresses
- Address N stores first byte
- Address N+1 stores second byte
- Pattern continues for larger data
Rule 3: Data Alignment
Multi-byte data follows specific storage rules
- 16-bit data: 2 consecutive bytes
- 32-bit data: 4 consecutive bytes
- Byte order follows Little Endian format
Little Endian Format - Intel's Byte Order
The 8086 processor uses Little Endian format for storing multi-byte data, which affects how programmers work with memory.
Little Endian Rule Explained
Definition:
"The least significant byte (lower byte) is stored at the lower memory address"
Why "Little Endian"?
- Term from Jonathan Swift's "Gulliver's Travels"
- Little-endians cracked eggs at the small end
- In computing: "little end" (LSB) comes first
16-bit Data Storage Examples
Example 1: Data = 1234H at address 5000H
| Address | Data Stored | Binary | Significance |
|---|
| 5000H | 34H | 00110100 | Lower byte (LSB) |
| 5001H | 12H | 00010010 | Higher byte (MSB) |
Example 2: Data = ABCDH at address 7000H
| Address | Data Stored | Binary | Significance |
|---|
| 7000H | CDH | 11001101 | Lower byte (LSB) |
| 7001H | ABH | 10101011 | Higher byte (MSB) |
Example 3: Data = 9876H at address 2000H
| Address | Data Stored | Decimal Value | Significance |
|---|
| 2000H | 76H | 118 | Lower byte (LSB) |
| 2001H | 98H | 152 | Higher byte (MSB) |
Little Endian vs Big Endian
| Format | Byte Order | Example (1234H) | Used By | Advantage |
|---|
| Little Endian | LSB first | 34H at 1000H, 12H at 1001H | Intel x86, ARM (optional) | Easy arithmetic operations |
| Big Endian | MSB first | 12H at 1000H, 34H at 1001H | Motorola, Network protocols | Intuitive reading |
Practical Problems and Calculations
Memory Address Calculations
Problem Set 1: Address Bus Calculations
Problem 1A:
Question: A processor has a 19-bit address bus. Calculate the maximum memory it can address in KB and MB.
Solution:
- Maximum addresses = 2^19 = 524,288
- Memory in bytes = 524,288 bytes
- Memory in KB = 524,288 ÷ 1024 = 512 KB
- Memory in MB = 512 ÷ 1024 = 0.5 MB
Problem 1B:
Question: How many address lines are needed to directly address 16 MB of memory?
Solution:
- Required memory = 16 MB = 16 × 1024 × 1024 = 16,777,216 bytes
- Find n such that 2^n ≥ 16,777,216
- 2^24 = 16,777,216
- Answer: 24 address lines required
Problem Set 2: Little Endian Storage
Problem 2A:
Question: Store the 16-bit data 8A5FH starting at memory address 4000H using Little Endian format.
Solution:
| Address | Data Stored | Explanation |
|---|
| 4000H | 5FH | Lower byte (LSB) at lower address |
| 4001H | 8AH | Higher byte (MSB) at higher address |
Problem 2B:
Question: Memory locations 6000H contains 3DH and 6001H contains 7BH. What 16-bit data is stored starting at 6000H?
Solution:
- Address 6000H = 3DH (Lower byte)
- Address 6001H = 7BH (Higher byte)
- Using Little Endian format: Higher byte first in value
- 16-bit data = 7B3DH
Problem Set 3: Data Transfer Performance
Problem 3A:
Question: Compare the number of memory accesses required to transfer 2000 bytes using 8086 vs 8088.
Solution:
- 8086 (16-bit data bus): 2000 ÷ 2 = 1000 memory accesses
- 8088 (8-bit data bus): 2000 ÷ 1 = 2000 memory accesses
- Performance ratio: 8086 is 2x faster for bulk transfers
- Time savings: 50% reduction in memory cycles
Summary and Key Takeaways
Essential Points to Remember:
Bus System Fundamentals
- Address Bus (20-bit): Determines 1 MB maximum memory
- Data Bus (16-bit): Enables 2-byte transfers per cycle
- Control Bus: Coordinates all system operations
Memory Calculations
- Formula: Memory = 2^(address bits)
- 8086 Range: 00000H to FFFFFH (1 MB)
- Unit Rule: 1 memory location = 1 byte
Performance Implications
- 8086 vs 8088: 2x speed advantage for 8086
- Data width: Directly affects transfer rate
- Memory cycles: Fewer cycles = better performance
Little Endian Storage
- Rule: Lower byte at lower address
- Format: LSB first, then MSB
- Intel Standard: Used throughout x86 family
Advanced Memory Banking Concepts
Memory banking extends the 8086's memory capabilities beyond the basic 1MB limit through sophisticated memory organization techniques.
Two-Bank Memory System
The most common banking implementation divides memory into even and odd address banks, enabling parallel access for improved performance.
Banking Performance Benefits
Extended Banking for Memory Expansion
Beyond the 1MB limit, extended banking systems use bank switching to access additional memory:
Bank Switching Principles:
- Window Mapping: Map 64KB windows to different physical banks
- Software Control: I/O port or memory-mapped bank selection
- EMS/XMS Standards: Standardized extended memory access
- Application Transparency: Bank switching handled by OS/drivers
Practical Banking Example:
System Configuration:
- Base Memory: 640KB (standard DOS)
- Extended Memory: 15MB (banked access)
- Bank Size: 64KB per bank
- Switching Method: I/O port 0x40
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