8086 Microprocessor Architecture and Features

8086 Microprocessor Internal Architecture - Foundation

The Intel 8086 microprocessor employs a sophisticated internal architecture designed around the concept of functional unit separation and pipelining. Understanding this architecture is fundamental to grasping how modern processors achieve high performance through parallel operation of different subsystems.

Architectural Philosophy and Design Principles

The 8086 architecture is built on several key principles:

• Functional Separation: Different units handle specific tasks independently
• Pipelining Concept: Overlapping instruction fetch and execution phases
• Bus Multiplexing: Sharing pins between address and data to reduce package size
• Segmented Memory Model: Efficient memory management through 64KB segments
• Register-Rich Design: Multiple specialized registers for different purposes

Two-Unit Architecture - BIU and EU

The 8086 is fundamentally divided into two independent but cooperating functional units:

Bus Interface Unit (BIU) - External Communication Hub

The BIU serves as the interface between the processor core and the external world, handling all bus operations and memory management:

BIU Components and Functions:

• Instruction Queue (6 bytes): First-In-First-Out buffer storing prefetched instructions
• Segment Registers (16-bit each):
  • CS (Code Segment): Points to current code segment
  • DS (Data Segment): Points to current data segment
  • SS (Stack Segment): Points to current stack segment
  • ES (Extra Segment): Additional segment for data operations
• Instruction Pointer (IP): 16-bit register pointing to next instruction
• Address Generation Unit: Combines segment and offset to create 20-bit physical addresses
• Bus Control Logic: Manages external bus operations and timing

Address Generation Process:

Pipelining in 8086 Architecture

The 8086 implements a two-stage pipeline through the separation of BIU and EU, allowing instruction fetch and execution to occur simultaneously. This represents one of the earliest implementations of instruction pipelining in microprocessors.

Pipeline Operation Principles:

• Temporal Parallelism: BIU fetches the next instruction while EU executes the current one
• Instruction Queue: 6-byte buffer allows continuous operation
• Branch Handling: Queue flushed on branch instructions
• Performance Gain: Up to 2× improvement in instruction throughput

Pipeline Performance Analysis:

Memory Banking and Segmentation Integration

The 8086 architecture supports advanced memory organization through segmentation and banking, enabling efficient memory utilization beyond the basic 1MB addressing limit.

Segmentation Architecture:

Banking Implementation:

Memory banking in 8086 systems allows access to extended memory through bank switching mechanisms:

• Two-Bank System: Even/odd address banking for improved bandwidth
• Interleaved Access: Overlapped memory operations
• Extended Banking: Software-controlled bank switching for >1MB
• Performance Benefits: Reduced memory access latency

Execution Unit (EU) - Computational Core

The EU is responsible for executing instructions and performing all computational operations. It operates independently of the BIU, enabling pipelined operation:

EU Components and Functions:

• 16-bit Arithmetic Logic Unit (ALU): Performs arithmetic and logical operations
• General Purpose Registers (16-bit each):
  • AX (Accumulator): Primary register for arithmetic operations
  • BX (Base Register): Used as base pointer for memory addressing
  • CX (Count Register): Loop counter and shift/rotate operations
  • DX (Data Register): I/O operations and multiplication/division
• Index Registers (16-bit each):
  • SI (Source Index): Points to source operand in string operations
  • DI (Destination Index): Points to destination in string operations
• Pointer Registers (16-bit each):
  • SP (Stack Pointer): Points to top of stack
  • BP (Base Pointer): Points to base of stack frame
• Flag Register (16-bit): Contains status and control flags
• Control Unit: Decodes instructions and controls execution sequence

Register Subdivision - 8-bit Accessibility:

The general-purpose registers can be accessed as 16-bit words or 8-bit bytes:

General Purpose Registers

• AX (Accumulator): Primary register for arithmetic operations. Can be used as AH (high byte) and AL (low byte)
• BX (Base Register): Used for addressing and as a general-purpose register. BH and BL available
• CX (Count Register): Used as counter in loops and string operations. CH and CL available
• DX (Data Register): Used in I/O operations and multiplication/division. DH and DL available

Segment Registers (16-bit)

• CS: Points to the segment containing the current code
• DS: Points to the segment containing data
• SS: Points to the segment containing the stack
• ES: Extra segment register for string operations

Memory Segmentation Model

The 8086 uses a segmented memory model to access more than 64KB of memory with 16-bit registers.

Physical Address Calculation

Formula: Physical Address = (Segment Register × 16) + Offset

Example Calculation:

Given: CS = 1234H, IP = 5678H
Physical Address = (1234H × 16) + 5678H
                 = 12340H + 5678H  
                 = 179B8H

Memory location accessed: 179B8H

Segment Override

By default, different types of memory references use specific segment registers:

• Code: CS:IP
• Data: DS:offset
• Stack: SS:SP or SS:BP
• String: ES:DI (destination), DS:SI (source)

Flag Register

The 16-bit flag register contains status and control flags that indicate the processor state and control its operation.

Status Flags

• Carry Flag (CF): Set when there's a carry out from the MSB
• Parity Flag (PF): Set when result has even number of 1's
• Auxiliary Carry Flag (AF): Set when there's a carry from bit 3 to bit 4
• Zero Flag (ZF): Set when result is zero
• Sign Flag (SF): Set when result is negative (MSB = 1)
• Overflow Flag (OF): Set when signed arithmetic overflow occurs

Control Flags

• Direction Flag (DF): Controls string operation direction
• Interrupt Enable Flag (IF): Enables/disables maskable interrupts
• Trap Flag (TF): Enables single-step debugging mode

Pipelining in 8086

The 8086 uses a two-stage pipeline to improve performance by overlapping instruction fetch and execution.

Pipeline Benefits:

• Increased Throughput: Instructions are fetched while others execute
• Better Resource Utilization: Both BIU and EU work simultaneously
• Reduced Idle Time: Minimizes processor waiting periods

Pipeline Stalls:

The pipeline may stall during:

• Jump instructions that change program flow
• Instruction queue empty conditions
• Memory access conflicts

Numerical Problems

Problem 1: Physical Address Calculation

Question: Calculate the physical address if DS = 2000H and the offset is 1234H.

Solution:
Given: DS = 2000H, Offset = 1234H

Physical Address = (Segment × 16) + Offset
                 = (2000H × 16) + 1234H
                 = 20000H + 1234H
                 = 21234H

Answer: Physical Address = 21234H

Problem 2: Maximum Memory Calculation

Question: What is the maximum memory that can be addressed by 8086?

Solution:
8086 has a 20-bit address bus
Maximum addressable memory = 2^20 bytes
                           = 1,048,576 bytes
                           = 1024 KB
                           = 1 MB

Answer: Maximum memory = 1 MB

Problem 3: Segment Size Calculation

Question: If a segment starts at 3000H, what is the last address in that segment?

Solution:
Segment starting address = 3000H × 16 = 30000H
Maximum segment size = 64KB = 65536 bytes = 10000H

Last address in segment = 30000H + 10000H - 1
                       = 3FFFFH

Answer: Last address = 3FFFFH

Key Features Summary

The 8086 microprocessor offers several advanced features for its time:

• 16-bit Data Path: Processes 16 bits of data simultaneously
• 1MB Memory Space: Can address up to 1 megabyte of memory
• Segmented Architecture: Efficient memory management through segments
• Rich Instruction Set: Over 100 instructions with various addressing modes
• Pipelining: Overlapped instruction fetch and execution
• Multiprocessor Support: Can work in multiprocessor configurations